Design and Analysis of Power Efficient 9t Adiabatic Sram Cell
نویسندگان
چکیده
Leakage power is becoming the dominant power component in deep submicron technology and stability of the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced feature sizes. A novel 9T SRAM cell design considering these leakage issues for ultra low power applications is proposed in this paper. The elementary cell structure of proposed adiabatic SRAM resembles behavior of static CMOS 4T-SRAM consisting of two high load resistors which is constructed of PMOS, a crosscoupled NMOS pair, NMOS switch which is necessary to restrict short circuit current and two trapezoidalwave pulses. From the simulation results, it has been shown that the average power dissipation of the proposed SRAM reduces by a factor of 98% with no performance degradation and energy is efficiently recovered using adiabatic operation and body bias. The simulation is carried out at 180nm technology. The stability of proposed SRAM is investigated using MATLAB. Keywords—Adiabatic Logics, Average power Dissipation, Body Bias , SRAM.
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